Difference: FredBackPlane (1 vs. 2)

Revision 22011-04-21 - PeterWinter

Line: 1 to 1
 
META TOPICPARENT name="MuECapture"
Changed:
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<
Hi, Peter,
I see. I was under the impression that you are using a DC-DC converter. So how critical is the range/stability around 3.3V?

In retrospect, I wish that we had used an onboard regulator for all parts (instead of almost all parts) as you suggest.

The two digital devices that use the 3.3V supply directly (flash memory and differential receiver for the control lines) are both specified to operate from 3.0 to 3.6 V. The differential op-amps (AD8132AR) on the analog side are specified from 2.7 to 5.5 V, and they nominally reject power supply oscillations by -70 dB (a factor of ~3000 in voltage amplitude).

Thanks,

-- Fred

Hi, Peter,

  • How recent was your measurement of 3 A of current? When I talked with Peter Winter last week, he told me that the power consumption in the lab was a little more than 4 A. (On the other hand, the power consumption on the negative supply is quite small: about 20 mA per module.)
  • The flash RAM for the FPGAs and the LVDS receiver are both connected directly to the +3.3V supply. The absolute maximum rating of the power supply voltage for these parts is +4 V. (Operation is not guaranteed at that voltage, only the absence of smoke.)
  • The negative power supply voltage, which is nominally -3.3 V, has been pushed down as far as -5 V in order to use a computer power supply (ATX standard). This worked quite well to drive a single module inexpensively.
  • A switching power supply should be fine. In general, that's what we've always used in various experiments with these boards. (The excellent pulse shape discrimination that we observed at Los Alamos used a switching power supply module on the positive side and a lab benchtop variable power supply on the negative side.)
  • The power supply pinout is shown in the attached image.

I'm quite curious what application you are planning for 10 FADC modules in your Mu2e test. When you have time, please do let me know.

Thanks very much,

-- Fred
------------------------------------------------------------------- Frederick Gray, Ph.D.  Assistant Professor of Physics / Physics Program Director Regis University, Denver, Colorado, U.S.A. +1 303-458-3564 / http://academic.regis.edu/fgray ------------------------------------------------------------------- 


Peter Kammel wrote: Dear Fred,

Vadim is looking whether Fermilab can put together the backplane bus for the FADC.

I lent him one of your FADCs, so that he can get experience reading it out
in his lab. I should have asked you before, but he was driving back this afternoon.
So I hope that it ok with you. Once you return home, we would appreciate
if you can send us one or two of the modified FADCs, so that we can set up a
3 FADC system at UIUC.


I have copied the power supply description from your draft paper.

1.4. Power supply
Power is supplied to the board through a
DIN 41612 type H15 connector on which only three
pins are used, for +3.3 V, ground, and a negative
supply (-3.3 V or -5 V). The connector also provides
some mechanical stability to hold the board in an
enclosure.
Three components directly use the +3.3 V power
supply: the differential receiver for control signals,
a programmable read-only memory (PROM) that
stores the FPGA program, and the differential frontend
amplifiers. For all other components, the supply
voltage is reduced by a UCC283-ADJ linear lowdropout
(LDO) adjustable regulator. Four of these
regulators are used, producing voltages of 1.2 V,
1.8 V (twice), and 2.5 V. The 1.2 V supply provides
the core voltage for the FPGA logic. One of the 1.8 V
supplies powers the digital side of the flash ADCs
and the logic in the Ethernet transceiver, while the
other is used exclusively for the analog functions of
the FADCs. This separation reduces the possibility
of crosstalk between the board’s digital functions
and the analog circuits.

We measured that one FADC needs about 3 Amps on the +3.3 V line.
That means for 10 FADC we would need 30 Amps.

As the negative voltage is only an offset, probably the current is very low.
Please send us the voltage pin assignment or refer us to a suitable elog.

If Fermilab suggests to provide a power supply, is a switched power supply
good enough or do you need a linear one.

What is the maximum voltage before damaging the circuit. If we have
suitable power supply operating below your max voltage it would be fine.
Otherwise, can we voltage limit the voltage on the backplane with
some diode switch to ground.
  • connector.png:
    connector.png
>
>
Please go to https://muon.npl.washington.edu/twiki/bin/view/Main/FredBackPlane
 
META FILEATTACHMENT attachment="connector.png" attr="" comment="" date="1243520776" name="connector.png" path="connector.png" size="28106" stream="connector.png" tmpFilename="/usr/tmp/CGItemp34994" user="PeterKammel" version="1"

Revision 12009-05-28 - PeterKammel

Line: 1 to 1
Added:
>
>
META TOPICPARENT name="MuECapture"
Hi, Peter,
I see. I was under the impression that you are using a DC-DC converter. So how critical is the range/stability around 3.3V?

In retrospect, I wish that we had used an onboard regulator for all parts (instead of almost all parts) as you suggest.

The two digital devices that use the 3.3V supply directly (flash memory and differential receiver for the control lines) are both specified to operate from 3.0 to 3.6 V. The differential op-amps (AD8132AR) on the analog side are specified from 2.7 to 5.5 V, and they nominally reject power supply oscillations by -70 dB (a factor of ~3000 in voltage amplitude).

Thanks,

-- Fred

Hi, Peter,

  • How recent was your measurement of 3 A of current? When I talked with Peter Winter last week, he told me that the power consumption in the lab was a little more than 4 A. (On the other hand, the power consumption on the negative supply is quite small: about 20 mA per module.)
  • The flash RAM for the FPGAs and the LVDS receiver are both connected directly to the +3.3V supply. The absolute maximum rating of the power supply voltage for these parts is +4 V. (Operation is not guaranteed at that voltage, only the absence of smoke.)
  • The negative power supply voltage, which is nominally -3.3 V, has been pushed down as far as -5 V in order to use a computer power supply (ATX standard). This worked quite well to drive a single module inexpensively.
  • A switching power supply should be fine. In general, that's what we've always used in various experiments with these boards. (The excellent pulse shape discrimination that we observed at Los Alamos used a switching power supply module on the positive side and a lab benchtop variable power supply on the negative side.)
  • The power supply pinout is shown in the attached image.

I'm quite curious what application you are planning for 10 FADC modules in your Mu2e test. When you have time, please do let me know.

Thanks very much,

-- Fred
------------------------------------------------------------------- Frederick Gray, Ph.D.  Assistant Professor of Physics / Physics Program Director Regis University, Denver, Colorado, U.S.A. +1 303-458-3564 / http://academic.regis.edu/fgray ------------------------------------------------------------------- 


Peter Kammel wrote: Dear Fred,

Vadim is looking whether Fermilab can put together the backplane bus for the FADC.

I lent him one of your FADCs, so that he can get experience reading it out
in his lab. I should have asked you before, but he was driving back this afternoon.
So I hope that it ok with you. Once you return home, we would appreciate
if you can send us one or two of the modified FADCs, so that we can set up a
3 FADC system at UIUC.


I have copied the power supply description from your draft paper.

1.4. Power supply
Power is supplied to the board through a
DIN 41612 type H15 connector on which only three
pins are used, for +3.3 V, ground, and a negative
supply (-3.3 V or -5 V). The connector also provides
some mechanical stability to hold the board in an
enclosure.
Three components directly use the +3.3 V power
supply: the differential receiver for control signals,
a programmable read-only memory (PROM) that
stores the FPGA program, and the differential frontend
amplifiers. For all other components, the supply
voltage is reduced by a UCC283-ADJ linear lowdropout
(LDO) adjustable regulator. Four of these
regulators are used, producing voltages of 1.2 V,
1.8 V (twice), and 2.5 V. The 1.2 V supply provides
the core voltage for the FPGA logic. One of the 1.8 V
supplies powers the digital side of the flash ADCs
and the logic in the Ethernet transceiver, while the
other is used exclusively for the analog functions of
the FADCs. This separation reduces the possibility
of crosstalk between the board’s digital functions
and the analog circuits.

We measured that one FADC needs about 3 Amps on the +3.3 V line.
That means for 10 FADC we would need 30 Amps.

As the negative voltage is only an offset, probably the current is very low.
Please send us the voltage pin assignment or refer us to a suitable elog.

If Fermilab suggests to provide a power supply, is a switched power supply
good enough or do you need a linear one.

What is the maximum voltage before damaging the circuit. If we have
suitable power supply operating below your max voltage it would be fine.
Otherwise, can we voltage limit the voltage on the backplane with
some diode switch to ground.
  • connector.png:
    connector.png

META FILEATTACHMENT attachment="connector.png" attr="" comment="" date="1243520776" name="connector.png" path="connector.png" size="28106" stream="connector.png" tmpFilename="/usr/tmp/CGItemp34994" user="PeterKammel" version="1"
 
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